1. Field of the Invention
The present invention pertains to an apparatus, a computer implemented method and a computer executable program for designing a semiconductor integrated circuit including a processor configurable in accordance with a target (configurable processor). In particular, the present invention pertains to a technology for aid to divide functions into portions implemented by hardware and portions implemented by software as an execution program from among software description in which the algorithm of a semiconductor integrated circuit is described.
2. Description of the Related Art
Conventionally, in a system LSI design of a System on Chip (SoC) installing a processor (configurable processor) in which instructions can be added and/or configurations can be changed according to a target, as for a designer, it is indispensable to describe a source program for an algorithm required of a system for development by using high-level languages, such as C programming language, and to perform a system simulation in a higher level in order to verify functions as the system.
More specifically, as shown in FIG. 1, the source program in which the algorithm is described is inputted in Step S901. In Step S902, the designer selects a configuration of the processor, performs compiling the source program, and performs the system simulation in the higher level, and then, in Step S903, the designer verifies whether or not required performance is achieved.
As a result of the verification in Step S903, if the required performance is not achieved, the designer obtains a profile at the source program level and locates a bottleneck to be implemented by hardware, in Step S904. Furthermore, in Step S905, the designer selects a portion to be replaced with hardware from among the functions described in the source program, that is, the designer divides the functions into the hardware and the software at the source program level, and rewrites the source program. The designer, in Step S906, creates a program for emulating the newly divided hardware function.
Then, the designer, in Step S902, retries the system simulation, and, in Step S903, verifies whether or not the required performance is achieved. As a result of the verification, if the required performance is achieved, the work for implementation, such as a tune-up the software, a high-level synthesis, a design by using manpower, and the like, is performed in Step S907.
The above-mentioned series of processing, such as the locating the bottleneck to be implemented by the hardware (Step S904), selecting the portion to be replaced with the hardware and writing the source program (Step S905), and creating the program for emulating (Step S906), is repeatedly performed until the system simulation result is satisfied. Therefore, the processing by using manpower, such as rewriting of the source program, correcting the simulation environment, and the like, became a burden, and the time and cost involved to the design were increased.
For this reason, an apparatus for supporting performance evaluation in an initial stage in the dividing work of hardware and software is disclosed in Japanese patent Laid Open Publication (Kokai) No. 2000-57188. This apparatus supports the performance evaluation by generating and displaying new hardware information and new software information based on hardware parts information and software parts information stored in a database, when a designer registers desired device as new parts on a screen.
Further, a methodology for smoothing the way to design by enabling a designer to select a library of a processor, a memory and a circumference circuit by using a graphical design editor, and for generating a circuit and software design environment based on the selected items is disclosed in a paper “Platform-Based Design Methodology; Platform Express”, Mentor Graphics Japan Corporation, News and View, February, 2002. (“Platform Express” is a trademark of Mentor Graphics Corporation.)
However, the apparatus disclosed in the publication No. 2000-57188 cannot display information in consideration of the influence upon the composition of a processor by selecting a portion replaced with hardware from an algorithm described in a source program and dividing functions. The apparatus therefore cannot design in consideration of performance of a configurable processor. Furthermore, the apparatus has no support function for improving a compiler and simulation environment. Therefore, since a human mistake at the time of environmental maintenance occurs, there is a problem of causing deterioration of design quality and protraction of a design period.
Although the function to improve the software design environment changed based on selection of hardware is shown in the above paper “Platform Express™ Platform-Based Soc Design and verification”, the function is not corresponding to the configurable processor, and there is no function to select a portion to be implemented by hardware from an algorithm described by the source program and to divide functions, which are necessity to the top-down design process for programming an algorithm required for LSI by using a high-level language. Therefore, it is not possible to correspond to the design from the algorithm description using the configurable processor. Thus, in the design from the higher level using the algorithm description, manpower, such as rewriting of the source program and correction of simulation environment, is needed, and there is a problem of causing deterioration of design quality and protraction of a design period.